This invention relates to vertical sync separators for television receivers, for example.
In the vertical blanking interval of a standard NTSC composite video signal, six serrated vertical sync pulses are provided for use by the vertical sync separator circuit of a television receiver. Typical separator circuits include an RC integrator which integrates the serrated vertical sync voltage. The integrator output is coupled to a comparator. When the integrated sync voltage exceeds a predetermined threshold level, the comparator generates an output pulse for synchronizing the vertical deflection circuit scanning current.
Such vertical sync separators are sensitive to noise superimposed on the serrated vertical sync pulses. The sensitivity to noise increases as the RC integrator charges toward the threshold level. Thus, when the integrator is charged to near the threshold level even very small amplitude noise signals of the same polarity as the serrated vertical sync pulse will cause early triggering of the separator, and noise signals of the opposite polarity subtract from the integrator charge and thereby delay triggering. The vertical synchronization is dependent upon the time at which the sync separator comparator triggers. In the presence of noise, the comparator threshold may be crossed and recrossed several times near the transition time. Since noise is unavoidable in a broadcast signal, the vertical synchronization is unstable and may jitter under normal operating conditions.
The integrator-type sync separator is particularly sensitive to noise pulses having a relatively long duration and high amplitude. The integrator operates upon such noise pulses as it would upon a vertical sync signal, and may produce output pulses falsely indicating the occurrence of a sync pulse in the interval between true sync pulses. This completely unstabilizes the deflection and results in vertical "rolling" of the displayed images.
A large body of art has developed for compensating for the deficiencies of the RC integrator sync separator. For example, some vertical count-down systems generate a vertical-rate signal independent of the vertical synchronizing signal for synchronizing the deflection. The signal produced by the sync separator is processed by the various count-down systems in a variety of manners to reconcile the variations in comparator triggering time. The reconciled time is then used to synchronize the independently generated vertical-rate signal.
The vertical count-down arrangements ameliorate the basic jitter problem of the RC integrator, but do not solve it. In ameliorating the jitter, these systems may become too sensitive to noise and may therefore fail to recognize synchronizing signals which are only slightly obscured. For example, U.S. Pat. No. 3,878,335 issued Apr. 15, 1975 to Balaban describes a vertical count-down synchronizing system. In the Balaban arrangement, the integrator output is applied to a comparator which produces a digital output representative of the polarity of the integrator output relative to a threshold level. The bilevel comparator output is applied to the input of an eight-bit shift register. Each bit in the shift register is coupled to a separate input terminal of an AND gate. The output of the AND gate goes high when the bilevel comparator output pulse is of the requisite duration to indicate the presence of a vertical sync signal.
In the presence of small amounts of noise near the bilevel comparator threshold, the comparator may, as mentioned, cross and re-cross the threshold several times, resulting in a comparator output in which the effect of the noise has been increased out of proportion to its magnitude. The shift register and AND gate are therefore unable to distinguish between small amounts of noise perturbing a sync signal and large-magnitude noise having the same general width as a sync pulse. Slight perturbations of the sync signal by noise then, result in a digital signal which does not match the ideal pulse. The count-down arrangement does not respond to such a perturbed sync signal and may not update its internal generator. Digital count-down arrangements thus may be seen to compensate for the excessive sensitivity of the RC integrator type of sync signal separator to small amounts of noise and for its response to low-frequency noise signals by ignoring all but substantially perfect sync pulses. This does not take advantage of the information available in sync pulses containing moderate amounts of noise.
It is advantageous to design a vertical sync detector or separator which provides increased noise immunity and relatively stable sync pulses in the presence of noise.